π§ CPO (Co-Packaged Optics) β κ΄ ν¨ν€μ§
horizon 1-3y Β· confidence MEDIUM Β· last_updated β
L0
κ±°μ trend
AI chip κ° κ΄ μΈν°μ»€λ₯νΈ μμ (μ κΈ° β κ΄ μ ν paradigm)
L1
μ°μ
μν©νΈ
μ€λ¦¬μ½ ν¬ν λμ€Β·κ΄ ν¨ν€μ§Β·κ΄ μ€μμΉ
L2
λ³λͺ© (Bottleneck)
- CPO ν¨ν€μ§ capacity λΆμ‘± (TSMC CoWoS νμ₯)
- κ΄ λͺ¨λ (transceiver) 800Gβ1.6T μ ν
- μ€λ¦¬μ½ ν¬ν λμ€ μμ° μμ¨
L3
1μ°¨ μν (Pure-play)
π°π· KR
π Global
TSMC 2330.TW
Broadcom AVGO
Marvell MRVL
Coherent COHR
L4
2μ°¨ μν (Picks & Shovels)
π°π· KR
π Global
Lumentum LITE
II-VI/Coherent COHR
Fabrinet FN
L5
μνκ³ (Ecosystem)
π Global
NVIDIA NVDA
Arista Networks ANET
π Sources
- TSMC 2026 tech symposium β CoWoS-L Β· CPO roadmap
- NVIDIA GTC 2025 keynote β NVL72Β·NVLink Switch κ΄ λμ
- Marvell 2025 AI Day β 1.6T transceiver
π Notes
CPOλ chip-to-chip κ΄ ν΅ν©. AI λ°μ΄ν°μΌν° power efficiencyΒ·latency
ν΄κ²° ν΅μ¬. 2027-2028 μμ°ν 본격. νκ΅ μ’
λͺ©μ λΉκ΅μ μ½ν¨.